I haven’t done more tests with the mods, but as stated in my previous post, main issue is the logic being powered by +5V on Cadet Sync Gen and the 27MHz VCXO being +3.3V only. So maybe using a logic level converter to go from +5V at the output of the PLL to +3.3V to feed the lag/lead filter just before the VC input of the VCXO could work, there will surely be a bit of propagation delay, though might be negligible enough.
Else, most logic chips have a Vcc/2 input threshold (here 2.5V) , so in most cases, a +5V powered logic chip can accept a +3.3V signal at its input fine. The only critical part here is the VCXO VC, that needs to be +3.3V, since it expects a linearly changing signal, so it requires to be in the right range for the genlock feature to work as it should.