Sure, here is the schematic.
Basically VC, +5V and GND are coming from the connector (J1) that is soldered in place of the existing VCXO.
There is a +3.3V regulator for the 27MHz VCXO (X1) that cannot be powered by +5V (from what I tested, it can, though better safe than sorry 
). One issue that I already mentioned above, is that the resting frequency of the VCXO is at Vcc/2 (so 1.65V), whereas the output of the PLL filter will be more about 2.5V (since it is powered by 5V), which is an issue for genlock.
The 27MHz output is going into a D-flip flop (U1) wired as a divide by 2, to get 13.5MHz. I’ve added an inverter (U2) at the output of the flip flop, as I couldn’t find a flip-flop with Q output in SOT23 format, only /Q, however I’m not sure if it is really needed.
About the gerbers, I’d prefer to test it a bit more before releasing it. Also, I think now that the varactor solution might be a simpler way to do it, may require some trimming of the VC going to the varactor cathode though but would solve the issue with the 27MHz VCXO needing to be powered by +3.3V.