Thanks for sharing details on the hardware/software, being working on my own sync gen, it is super interesting to see!
Also great to see some love for Lattice FPGAs, I started my project using a Xilinx Coolrunner CPLD (as it is used on your older generations of modules iirc), then they are a little small in terms of macrocells/LUTs, so Eric Schlappi convinced me to look into the iCE40. It asks for a few more extra support components (SPI Flash and 1.8V regulator in addition to the 3.3V one), but the UP5K part comes in QFN package (which can be soldered by hand), has about 5K LUTs and is supported by the iCEstorm open source toolchain.
I was tempted using LMH1982 for the clock generator at first, though they’re quite expensive, so went for the PLL+VCXO as shown on Cadet I, looks like that what you’re using here too right? Also, we can see that the flash chip isn’t populated, I presume you’re writing the bitstream directly to the FPGA SRAM?
Hope I’m not annoying with my questions/sharing about my stuff, I’m pretty new to FPGAs and been learning through resources online until now, then this is pretty exciting to see a video sync generator implementation to me!
Here is the board I did, in DIP40 format to be used in DIY projects, with regulators at the top, then sync extractor, PLL+VCXO, iCE40 and finally flash (pardon the poor hand soldering, those tightly spaced 0603 were not super easy to fit). It is greatly inspired by iCEbreaker/UpDuino devboards.
From the time base, we can see that the pulses occurs every ~64us, so would be either 480i or 576i format. Then from the length of the pulses (~10us) we can guess that this is a blanking signal (and the continuous line on the left would be vertical blanking).