100n bypass cap for LM1881 and in general any V+ or V- pin on every IC. Place it adjacent to the power pin.
If the goal is to reset VCO, S&H, etc. then you do not really need the monostable part (74HC4538.) Just use the CSYNC output as HSYNC. The periods during which CSYNC looks different from HSYNC are during scanlines in the vertical blanking interval (meaning we never see them, any signal in those periods is removed at the output encoder.)
So in your cases listed (resetting a VCO), you can remove the 74HC4538 and just use CSYNC as HSYNC.
Cases in which you’d need the monostable include a genlock clock PLL circuit (like Cadet I).
LMH1980 is the preferred sync separator part for Gen3 stuff, if you care about HD syncs! It also has separate HSYNC output, which is handy. Just follow the circuit in the datasheet. It only comes in an SMT package size though.
re: Buffered outputs… these days we strongly recommend you include rear video sync input/buffered pass thru like this on each module that needs it, and just include HSYNC/VSYNC/OFF switch on the frontpanel (rather than patching HSYNC and VSYNC around). That would then select from the LM1881 TTL outputs to control whatever switch is in your VCO circuit directly. This is how the new LZX oscillator works for example – there is a frontpanel sync input, but it is OR’ed with the HSYNC/VSYNC being generated by the sync extraction circuit internally. I should post some application examples.