I have been simulating a few simple circuits that rely only on the outputs of the LMH1980 SD/HD Sync Separator IC, which is heavily used throughout the Gen3 modular. I’m just sharing some notes as I go.
Frame Sync Extractor
What do we do if we want a pulse that starts at the beginning of each frame? We can’t use VSYNC, as in interlaced formats it pulses twice per frame, at the start of each field. This simple circuit uses the ODD/~EVEN~ field flag, VSYNC, a NOT gate and an AND gate to create a positive-going pulse at the start of each frame. This signal is useful for feeding to clock dividers or sequencer clocks. Since the ODD/~EVEN~ flag is high when the input format is progressive, all of the VSYNC pulses are passed to the output.
Trisync/Csync Regenerator
HD sync formats require a tri-level sync pulse with both negative and positive going spikes, instead of just the negative pulse of the SD formats. The circuit below generates +/-300mV Trisync or -300mV Csync and buffers them for distribution to the sync inputs in your system. Note that the SD/~HD~ flag outputs are used to disable the use of HSYNC as the positive trisync level when SD video is detected.
It can probably implemented with less logic gates; I am only being careful here that propagation delay is identical relative to both sync signals.
Interlacing & Activity Detector
Sometimes you want a steady logic signal indicating whether video sync is being received, or when interlaced video is detected. When the Odd/~Even~ flag goes low, we retrigger the interlaced flag, as this event is evidence that our video source is interlaced. After a few fields without any falling Odd/~Even~ edges, the monostable resets and Progressive is detected. The activity detect works the same way – it just checks for falling edges on the input. These circuits are handy to drive LEDs or control other states.
