LZX Status Update 6/25/2022

This shit right here is gettin me fuckin pumped.
:popcorn:

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dang, never seen a portable vectorscope like that before. cool stuff!

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color bars end up being such a fun input to the video synth
glad to see it built in! otherwise it would have just ended up a still on our TBC2
hopefully some more people will take the time to really get to know chroma key on the memory palace with these bars

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Yes, test patterns are great. I have a Kramer VGA downscaler that generates a test pattern when there’s no VGA input. As I usually have no VGA sources, I use it mainly as a pattern generator. It’s great when I need a complex pattern and I’ve run out of modules to patch something up - or I’m just feeling lazy.

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Yes, especially if we are just rendering a still frame, it’s easy to have all kinds of software generators in TBC2. Here is the basic RGB ramps generator. All of this will get ported back to Memory Palace at some point.

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Thanks Lars! Updates like this are greatly appreciated and keep us super stoked and involved with your internal progress along the way as well as keeping our expectations in check and anxiety down in regards to what is happening and when to expect it, etc… great work!

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I think a development diary approach tends to work well for that! So I am going to try to keep this thread updated weekly and at any eventful milestones.

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Forget if this has been shared before, but if anyone needs some down-and-dirty color bars (for fun stuff), a ramp + Castle ADC works great.

Output:

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Just a technical note: That technique works well for 100% color bars, but most vector scopes will expect 75% levels (0.75V) for their calibration squares. In this case, since it’s TBC2’s DAC generating the RGB source, we can set a very specific RGB value for each bar – this helps in the calibration use case. Either method works, for a creative use case of course!!

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WANT TBC

(Is this funny? it seemed funny when I thought of it but by the time I completed it, it seems kinda dumb. I was originally thinking of Billy Idol but this had the text on it)

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You’re not alone. I too have heard Sting singing “I want my TBCeee!” for quite some time. :laughing:

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Ha ha, I played live visuals at a gig last week & an older gentleman walked in during the soundcheck. When he saw my visuals, for some reason he mentioned this exact song :smiley:
But it took us a while to think of the band name, funnily enough the album title came quickly to mind. I absolutely loved this song & video as a kid, as well as their other hit with some wacky video editing, “Walk of Life” :slight_smile:

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We had a quiet week this week, with steady ESG3 progress. Jonah tackled some pre-flight QA checks on the first batches of hardware modules while I iterated through firmware builds with lots of small tweaks – mostly related to the composite output’s subcarrier, and improving horizontal phase lock under all cases. That’s all looking great and it looks like we’ll be shipping some units soon.

This is a first time for us, doing a CVBS output with a locked subcarrier (previous encoder designs have used a free running crystal.) We’re using some of the PLL and DSP blocks in the Lattice iCE40LP5 FPGA to generate subcarrier clocks for NTSC and PAL. Since the PLL is based on the same 27MHz pixel clock used to generate the other sync signals: hsync, vsync, avid, etc, we can conform to broadcast standards for a locked synchronous subcarrier.

So in addition to the new HD modes, there is a substantial quality upgrade to this encoder in respect to the CVBS output, too!

When working on the VHDL code that compiles into the FPGA’s firmware, it can be a bit of a head shift compared to the C++ application code I’ve been writing for TBC2. It all gets compiled into real time logic, instead of processor instructions! I like VHDL a lot because you are describing a circuit, and so it feels natural to me. Here’s a process block that detects whether or not a sync signal is connected into the sync input jack, and also determines if the video source is interlaced:

process(i_clk)
  begin
    if rising_edge(i_clk) then
      s_clk_cnt <= s_clk_cnt + 1;
      s_csync_ff <= i_csync;
      s_csync_ff2 <= s_csync_ff;
      s_interlaced <= s_interlaced or not i_oddeven;
      if (s_csync_ff = '0' and s_csync_ff2 = '1') or (s_csync_ff = '1' and s_csync_ff2 = '0') then
        s_csync_cnt <= s_csync_cnt + 1;
      end if;
      if s_clk_cnt = 0 then
        s_o_interlaced <= s_interlaced;
        if s_csync_cnt > 0 then
          s_o_detected <= '1';
          s_csync_cnt <= 0;
        else
          s_o_detected <= '0';
        end if;
      end if;
    end if;
  end process;


triggering the scope off the video sync pulse, quadrature phases can be observed in the locked colorburst

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jesus, that scope shot is perfect

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I had some phase and DAC scale corrections to make to DSG3 this morning, and our 10-bit ramp generators are now looking great.

Here you can see some timing discontinuities I needed to fix – vertical reset line is in the wrong spot, and the vramp resets at the wrong phase:

Waveforms on the scope:

Enjoying a DSG3+ESG3 mini synth/pattern generator!



A couple quick shots in 1080p30 (excuse the moire):


We’re now at a point where I’m personally satisfied with where we are on both of these modules, and would be happy if firmware shipped in this state – but I need to meet with the team on Monday to assess where we are before I start promising shipment dates. This is a very big milestone though, as it puts both projects back into the workshop/production team’s priority queue.

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great to see such progress Lars - keep up the good work!

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I took a break from ESG3/DSG3 testing to play with a couple new prototypes today (Keychain, triple hard key generator and Contour, triple differentiator). Here’s DSG3 → Keychain → Contour → ESG3 in 1080p30.

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thank you for all the recent communications! I’m super interested in seeing the panel layout for contour.

how has that seetec monitor been working out?

It is really nice to see this kind of progress happening :slight_smile:

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@creatorlars , thank you for sharing your progress.
I’m looking forward to using ESG3! :heart_eyes:
And I’m curious about the Expedition modules that works in HD workflow…
Can you tell us about the Expedition module(s) that obviously doesn’t work in HD workflow at this time?

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